1. Technical Field
The present invention relates to a multi-port semiconductor memory device and a method for accessing and refreshing the same, and more particularly, to a multi-port semiconductor memory device and a method of performing efficient refresh and access right assignment on a shared memory area of the memory device.
2. Discussion of Related Art
DRAM (dynamic random access memory) is widely used as a semiconductor memory device for increasing integration density in a semiconductor substrate. In DRAM, one memory cell includes one select transistor and one data storing capacitor. Because charges are leaked through the storage capacitor and the select transistor, DRAM requires periodic refreshing to recharge the charges in its cells. Accordingly, semiconductor memory devices such as a DRAM need refresh control circuits for controlling operations related to refreshing the memory cells.
There are many known methods that are widely used to refresh memory cells in semiconductor memory devices such as DRAM.
First, in an RAS only refresh (“ROR”) method, cells are refreshed by enabling a row address strobe (RAS) signal while a column address strobe (CAS) signal is kept at a precharge level. During this refresh operation, external refresh addresses need to be provided to a memory device, and address buses connected to the memory device are not allowed to be used for other purposes.
Another type of refresh method is an automatic refresh method, also known as a CAS Before RAS (“CBR”) refresh method. In the previous mode of operation, an external RAS signal is enabled when memory cells are accessed in preference to an external CAS signal. On the other hand, in the automatic refresh method, a CAS signal is enabled in preference to an RAS signal to recognize a refresh mode. That is, the CAS signal is generated at a low level prior to the RAS signal being generated a low level. In this method, refresh addresses are internally generated by a refresh address counter in the DRAM and the refresh address counter cannot be externally controlled.
At present, DRAM provides a self refresh mode to reduce the amount of current consumed in the refresh operation. A start cycle in this mode is the same as that in the automatic refresh method. Specifically, when CAS and RAS signals are both kept at an active state (e.g., a low level) during a predetermined period of time (e.g., 100 μm), a self refresh operation is performed in which data stored in all memory cells are read and amplified during a given refresh period using a refresh timer and are then restored in the memory cells. However, during this operation, normal operations (e.g., read and write operations) are interrupted so that the refresh operation is not disrupted. In the self refresh method, a refresh timer and a refresh address counter in the DRAM automatically perform required refresh operations using their clock signals without using external clock signals. These refresh techniques are disclosed in U.S. Pat. Nos. 4,809,233, 4,939,695, 4,943,960, and 5,315,557.
This does not create a problem when the semiconductor memory device performing the refresh operation includes only one input/output port having various sets of input/output pins to communicate with an external processor. That is, in a single-port memory device, all memory banks constituting a memory array are accessed via the one port. Thus, the refresh operation can be performed according to command signals that are input via the port.
As mobile technology has recently been further developed, multi-port semiconductor memory devices having dual-ports or multiple ports has been introduced to meet the demands of this new technology. In multi-port semiconductor memory devices, communication is performed via a plurality of processors, and a plurality of memory cells can be simultaneously accessed via a plurality of input/output ports. However, unlike the single port devices discussed above, multi-port semiconductor memory devices may encounter problems during refresh operations because they include shared memory areas that are accessible via the plurality of input/output ports. For example, when a self refresh operation is performed through an input/output port having an access right to access the shared memory area, the shared memory area cannot be accessed via another input/output port without current access privileges. Thus, there is a need for efficient refresh and access right assignment via each input/output port.